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5). It is useful to define the sum and carry as a function of some intermediate signals, g = xy carry generate, and p = x ⊕ y carry propagate. Note that the functions g, p , are not dependent on the third input z , which is intended for the input carry. A carry output is generated by the full adder or the carry input z is propagated. 5), yielding carry = g + pz sum = p ⊕ z . 7 Digit-serial adder obtained by unfolding of a bit-serial adder. To reduce the critical path, the carries can be calculated in advance using the Carry-Look-Ahead (CLA) technique [72].

The Platch is propagated backwards into the data path and split the carry-chain into two paths with equal logic depths. The latch level pipelining will reduce the ripple in the carry chain and enable merging between the latches and logic enhancing the throughput, as shown by comparing the throughputs in Fig. 16 and Fig. 20. 10 Modular digit-serial adders based on serial prefix ripplecarry adders. 2 Digit-Serial Carry-Look-Ahead Adders To reduce the logic depth a parallel prefix adder may be used.

LM 0 is suitable for implementations with static CMOS using standard cells without pipelining, LM 1 corresponds to implementation with one pipeline register or using dynamic logic styles with merged logic and latches, and finally LM 2 which corresponds to pipelining internally in the adder suitable for standard cells implementation. It was generalized in [30] for digit-serial arithmetic and introducing pipeline registers after each M additions. 5) where n Adder is the number of adders between each pipeline register.

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Implementation of digital-serial filters by Magnus Karlsson.

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